Calypto Announces Promotion of Thomas Bollaert to Vice President of Applications Engineering

SAN JOSE, Calif., – May 15, 2013 – Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, today announced that Thomas Bollaert has been promoted to the role of VP of Applications Engineering.  Thomas, a seasoned professional with over 17 years of experience in EDA, joined Calypto in 2011 and has been leading the Application team in his role as Sr. Director of Application Engineering.  Before holding this position, Thomas was the product marketing manager for Mentor’s high-level synthesis group, successfully growing the Catapult product line to the number one position.

“In his role as Sr. Director of Application Engineering, Thomas, with the aid of his team, worked closely with the sales team to sharpen the company’s focus on customer success,” said Sanjiv Kaul, President and CEO at Calypto. “Thomas and his team play a major role in taking our products mainstream and making Calypto a vital partner to our customers. The Applications team is critical to helping our customers successfully deploy our products and gain competitive advantage.”

Prior to his role as product marketing manager for Catapult, Thomas held various positions in Europe including technical sales and product marketing at Summit Design, Innoveda and Cadence Design Systems. Thomas received his master degree in electronic engineering from ESIEE Paris, Ecole Supérieure d’Ingénieurs en Electronique et Electrotechnique, where he specialized in DSP, digital IC design and embedded systems architectures.

About Calypto’s Products

Catapult high-level synthesis, SLEC® (Sequential Logic Equivalence Checking) and PowerPro platforms are used to design, verify and optimize complex SoC and FPGA designs by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto’s products enable engineers to dramatically improve design quality and reduce power consumption of their SoC while significantly reducing overall design and verification time.

Calypto will be highlighting their products in booth # 1247 at the upcoming Design Automation Conference (DAC),  June 2 – 7, 2013 in Austin, Texas.  To register for a Calypto suite demonstration at DAC, please visit

About Calypto

Calypto® Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization.  Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE‐SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America. 

Catapult, Calypto, PowerPro and SLEC are registered trademarks of Calypto Design Systems Inc. All other trademarks are property of their respective owners.

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