High-performance, power-efficient memory solution designed for today’s data centers
SUNNYVALE, Calif. — (BUSINESS WIRE) — February 7, 2017 — Rambus Inc. (NASDAQ: RMBS) today announced the availability of its High Bandwidth Memory (HBM) Gen2 PHY developed for GLOBALFOUNDRIES high-performance FX-14TM ASIC Platform. Built on the GLOBALFOUNDRIES 14nm FinFET (14LPP) process technology, the Rambus HBM PHY is aimed at networking and data center applications and designed for systems that require low latency and high bandwidth memory. This PHY is fully compliant with the JEDEC HBM2 standard and supports data rates up to 2000 Mbps per data pin, enabling a total bandwidth of 256 GB/s to meet the needs of today’s most data-intensive tasks.
“Data center needs are continuously changing and we are at the forefront of delivering memory interface technology designed to meet today’s most demanding workloads,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces division. “Through our collaboration with GLOBALFOUNDRIES, we are delivering a comprehensive and robust solution for high-performance data center and networking applications. Our HBM offering will allow data center solution developers to bring high performance memory closer to the CPU, thus reducing latency and improving the system throughput.”
“With the rise of cloud computing and the growing needs of Big Data, the computing power of data centers is burdened more than ever and hardware manufacturers are being called upon to deliver new solutions that can meet these challenges,” said Kevin O’Buckley, vice president product development GLOBALFOUNDRIES. “Working together with Rambus enables us to provide ASIC solutions to our customers with increased memory capacity and bandwidth, with improved power efficiency. This HBM innovation complements other advanced chip to chip interfaces in our ASIC platform, including our industry leading 56G Long Reach SerDes technology.”
The Rambus HBM PHY delivers high performance with lower power consumption when compared to other memory solutions. It combines 2.5D packaging with a wider interface (1024 bits) at a lower clock speed, which results in a higher overall throughput while remaining energy efficient for even the most high-performance computing applications. Rambus experts perform complete signal and power integrity analysis on the entire 2.5D systems to ensure all signal and thermal requirements are met.
The HBM PHY is another key component in Rambus’ memory and SerDes high-speed interface IP portfolio for networking and data center applications. For additional information on Rambus Memory and Interfaces solutions, please visit rambus.com/memory-and-interfaces.
About Rambus Memory and Interfaces Division
The Rambus Memory and Interfaces division develops products and services that solve the power, performance, and capacity challenges of the communications and data center computing markets. Rambus enhanced standards-compatible and custom memory and serial link solutions include chips, architectures, memory and SerDes interfaces, IP validation tools, and system and IC design services. Developed through our system-aware design methodology, Rambus products deliver improved time-to-market and first-time-right quality.
About Rambus Inc.
Rambus creates innovative hardware and software technologies, driving advancements from the data center to the mobile edge. Our chips, customizable IP cores, architecture licenses, tools, software, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile, consumer and media platforms. At Rambus, we are makers of better. For more information, visit rambus.com.
Agnes Toan, 408-462-8905