Intel Technology and Manufacturing Day in China Showcases 10 nm Updates, FPGA Progress and Industry’s First 64-Layer 3D NAND for Data Center

September 18, 2017 - Intel delivered key updates at its Technology and Manufacturing Day held in Beijing, China, on Sept. 19. Disclosures included power and performance updates for Intel’s 10 nm process, high-level plans for Intel’s first 10 nm FPGA, and an announcement that the company is shipping the industry’s first commercially available 64-layer 3D NAND for data center applications.

Stacy Smith, group president of Manufacturing, Operations and Sales at Intel Corporation, displays a 10 nm “Cannon Lake” wafer featuring the world’s tightest transistor and metal pitches during the company’s Technology and Manufacturing Day in Beijing on Sept. 19, 2017. (Credit: Intel Corporation)

“Intel manufacturing processes advance according to Moore’s Law, delivering ever more functionality and performance, improved energy efficiency and lower cost-per-transistor with each generation,” said Stacy Smith, group president of Manufacturing, Operations and Sales. “We are pleased to share in China for the first time important milestones in our process technology roadmap that demonstrate the continued benefits of driving down the Moore’s Law curve.”

Press Kit:  Leading at the Edge: Intel Technology and Manufacturing

Smith added that Intel’s ability to advance Moore’s Law – to make products less expensive and more capable every year – is the company’s core competitive advantage. Intel’s role has been, and will continue to be, that of the technology leader driving Moore’s Law, and today, Intel has about a three-year lead in process technology. For more, read Smith’s editorial,  “Moore’s Law: Setting the Record Straight.”

Demonstrating Intel’s technology lead, Intel Senior Fellow Mark Bohr presented specification updates showing Intel’s 10 nm is a full generation ahead of other “10 nm” technologies in terms of both transistor density and transistor performance. Intel’s  10 nm technology has the world’s tightest transistor and metal pitches, created with hyper scaling, for the highest density in the industry. Hyper scaling is a term used by Intel to describe the 2.7x logic transistor density improvement attained on the company’s 14 nm and 10 nm processes. And, for the first time, Intel’s “Cannon Lake” 10 nm wafer was on public display.




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