SystemVerilog Parser Serves as Front End to Innergy Systems’ Integrated Power Analysis Platform
ALAMEDA, CALIF. –– October 10, 2018 –– Verific Design Automation today announced Innergy Systems licensed its Parser Platform to serve as the front end to its new Power Analysis Platform that combines quick-debug power analysis with fast power model generation.
“To say that Verific enabled Innergy Systems would be an understatement,” avows Ninad Huilgol, Innergy’s founder and chief executive officer. “Without its parser platform, our development cycle would have been immeasurably extended. Integrating the Verific front end with our Power Analysis Platform gave us the thrust we needed to deliver our software ahead of our project schedule.”
Innergy’s Power Analysis Platform integrates within an existing chip design flow. It builds fast power models earlier in the design cycle, avoiding late-stage power complications, and includes power analysis for quick debug, power analytics for model-based power exploration and system-level power exploration to reduce power and increase performance.
“Performance and power are operative words at Innergy Systems,” observes Rick Carlson, Verific’s vice-president of sales. “Providing our parser platform to a company as committed to both gives us a great deal of satisfaction.”
Verific’s SystemVerilog, VHDL and universal power format (UPF) Parser Platforms are used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping and design-for-test applications. Its Parser Platforms are distributed as C++ source code and compile on all 32 and 64 bit Unix, Linux, Mac and Windows operating systems.
About Innergy Systems
Innergy Systems of Sunnyvale, Calif., is staffed by experienced technical professionals designing a comprehensive Power Analysis Platform that combines power analysis for power debug and predictive analytics for fast exploration using fast power models generated by the tool. Founded in 2015, Innergy Systems is a member of the IEEE P2416 System Level Power Modeling Standards Committee. For more information, visit www.innergysystems.com
About Verific Design Automation
Verific Design Automation’s Parser Platforms are in production and development flows at EDA, FPGA and semiconductor companies worldwide, from emerging companies to established Fortune 500 vendors. Its software enables project groups to develop advanced EDA products quickly and cost effectively. With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 60,000 copies of its software since its founding in 1999.
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