"Our work through the InSequence program allows us to combine two powerful design technologies and offer our mutual customers the ability to explore power optimization at the architecture level," said Simon Napper, Synfora president and CEO. "This combination provides the user with unequaled insight into performance, area, and power for advanced SoCs early in the design, when analysis and design tradeoffs can have maximum impact."
PICO Express bridges the SoC design productivity gap by enabling the automatic generation of optimal architectures and synthesizable RTL from untimed C algorithms. As a result of using PICO Express, designers achieve significant reductions in the cost and risk of designing a SoC while being able to innovate and differentiate their end product. By integrating PICO Express with Sequence's PowerTheater, users can now generate multiple trial implementations and then run PowerTheater to estimate power at RTL and, later, at the gate level. The generated power data allows users to examine tradeoffs for performance, area, and power to reduce design iterations and optimize the design's power profile.
"By accelerating the early analysis of performance, area, and power, we provide a power-aware, higher level of productivity for SoC design," said Holly Stump, Sequence vice president of marketing. "Our collaboration with Synfora promises to provide breakthrough competitive benefits for designers in power-sensitive markets."
The integrated flow is now available; interested parties may contact either Sequence or Synfora for additional information.
Synfora is the latest in a series of InSequence partnerships, joining a variety of EDA vendors, foundries, IP providers, design services, platform vendors and universities.
PowerTheater is the industry standard for low-power design at RTL. Capabilities include accurate RTL power analysis closely correlated to actual silicon; power management tools that allow designers to reduce power at RTL using "what-if" scenarios and make early tradeoffs at the architectural level; power vector forward technology to select vectors for downstream analysis, feeding them to later stages of the design cycle for gate-level verification and voltage-drop analysis; and gate-level power verification, preventing power creep.
Founded in 2003, Synfora Inc. is the leading provider of application engine synthesis (AES) software used to design complex systems-on-chips (SoCs) for integrated consumer devices. Synfora's technology helps to reduce fixed design costs and dramatically speed chip development and time-to-market. Synfora serves customers worldwide in the audio, video, imaging, wireless, and security segments of the IC design market. The company's investors are ATA Ventures, Foundation Capital, and U.S. Venture Partners. For latest information on Synfora, please visit http://www.synfora.com.
Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence's power and signal-integrity software solutions give customers the competitive advantage necessary to excel in aggressive technology markets, despite the demanding complexity and time-to-market issues of nanometer design. Sequence serves over 150 customers worldwide, in application segments such as consumer, wireless, mobile computing, multimedia, cell phones, digital cameras, network-on-chip processors, and other power-sensitive markets. The company was named by Reed Electronics as one of the top 10 companies to watch in the electronics industry, and was recently selected as one of high-tech's Top 100 companies by siliconindia magazine. Sequence has worldwide development and field-service operations and is privately held. Please see sequencedesign.com.
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Sequence Public Relations
Jim Lochmiller, 541-821-3438