RDC Semiconductor Selects Virage Logic’s All Digital Intelli™ DDR3 PHY for Next-Generation SOC
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RDC Semiconductor Selects Virage Logic’s All Digital Intelli™ DDR3 PHY for Next-Generation SOC

Virage Logic’s Correct-by-Construction All Digital DDR3 PHY Enables RDC to Optimize Time-to-Market on 65nm Process

FREMONT, Calif. & TAIPEI, Taiwan — (BUSINESS WIRE) — July 22, 2010Virage Logic Corporation (NASDAQ: VIRL), the semiconductor industry's trusted IP partner, today announced that RDC Semiconductor Co., Ltd of Hsinchu, Taiwan has chosen the Intelli all digital, correct-by-construction DDR3 PHY+DLL for the next-generation RDC IAD Processor Platform targeting the high volume net-based consumer electronics (CE) market. Implemented on a 65-nanometer (nm) process technology, the Intelli DDR3 PHY+DLL solution enables RDC to meet 1.6 Gb/s data rates for DDR3 interface solutions, consuming less power and requiring a smaller area compared to traditional analog solutions. The Intelli DDR3 PHY+DLL solution offers RDC a semi-custom approach, where the PHY macro dimensions can be tailored to optimize the memory subsystem to meet particular market applications.

RDC is targeting one of the highest growth segments of the CE market. According to research firm Strategy Analytics, net-based application shipments jumped 79 percent last year to 30.2 million units and the market is poised to continue growing this year. The Milton Keynes, United Kingdom (UK) research firm said that the North American and Western European regions propelled the market's growth. In the United States (US), carriers including AT&T Mobility, Verizon Wireless and Sprint Nextel, have begun subsidizing net-based applications (with the purchase of a two-year mobile data plan) and carrying the devices in their retail outlets. Thus, along with smartphones and data cards, net-based applications with built-in, wide-area wireless capabilities have helped fuel mobile data traffic growth. The carriers have been selling net-based applications for between $150 and $200 when paired with a two-year data plan contract.

“We are thrilled that RDC Semiconductor chose Virage Logic for this net-based application System-on-Chip (SoC) design,” said Dr. Yankin Tanurhan, vice president and general manager for Virage Logic’s Processor, SoC Infrastructure, Application Specific IP (ASIP) and NVM Solutions business units. “One of the attractions of this solution beyond performance, power, and area, is that the Intelli DDR2/3 PHY+DLL includes system-level knowledge to deliver automated capabilities that can signal potential variations in silicon, package and/or board design, and manufacturing.”

“The Virage Logic solution was particularly advantageous for RDC because we had to meet a tight time-to-market window,” said Jacky Tsai, manager, marketing department at RDC Semiconductor Co., Ltd. “Virage Logic’s DDR2/3 PHY+DLL met the size, power, and performance requirements for our next-generation SoC and it was implemented on a 65nm process, which was the foundry and process node that our engineering team had qualified for this design. This perfect combination of factors made our choice very easy.”

About Virage Logic’s Intelli DDR2/3 PHY+DLL

Virage Logic’s Intelli PHY+DLL is a flexible and advanced solution for DRAM Physical Layer Interfaces (PHY) for ASIC and SoC designers requiring high-performance from a memory interface using the least amount of area. The Intelli PHY+DLL supports standard SDRAM, and DDR SDRAM, as well as a wide variety of standards for each type, including single data rate JEDEC standard SDRAM and Mobile SDRAM, double data rate JEDEC standard SDR, DDR1/2, DDR2/3, DDR3, MobileSDR, LPDDR and LPDDR2 DRAM. The Intelli PHY+DLL is designed for easy integration, and includes features such as DQS squelch.

The DLL portion of the solution is an all digital design for easy integration, test, support, and migration to new process technologies. The digital solution also provides lower power, smaller die size, and superior control for temperature and supply variations, with reduced noise immunity for very low jitter operations.

The Intelli DDR 2/3 PHY+DLL is an all digital PHY+DLL solution providing the high-performance and resolution required to meet 1.6 Gb/s data rates for DDR3 interface solutions. The all digital PHY+DLL solution provides maximum portability to different technologies and consumes lower power and smaller area as compared to traditional analog solutions.

About Virage Logic

Virage Logic is a leading provider of semiconductor intellectual property (IP) for the design of complex integrated circuits. The company's highly differentiated product portfolio includes processor solutions, interface IP solutions, analog solutions, SoC infrastructure IP solutions, embedded SRAMs and NVMs, embedded test and yield optimization solutions, logic libraries, and memory development software. As the semiconductor industry's trusted IP partner, more than 400 foundry, IDM and fabless customers rely on Virage Logic to achieve higher performance, lower power, higher density and optimal yield, as well as shorten time-to-market and time-to-volume. For further information, visit http://www.viragelogic.com.

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